It is not necessary for the target to be a file it could be just a name for the recipe, as in our example. On the other hand, a prerequisite can also be a target that depends on other dependencies: final_target: sub_target final_target.c To summarize, below is the syntax of a typical rule: target: prerequisitesĪs an example, a target might be a binary file that depends on prerequisites (source files). The target, prerequisites, and recipes together make a rule. The recipe uses prerequisites to make a target. The command echo 'Hello World' is called the recipe. For the sake of simplicity, we have not defined any prerequisites in this example. The prerequisites or dependencies follow the target. In the example above, say_hello behaves like a function name, as in any programming language. Now run the file by typing make inside the directory myproject. Create a empty directory myproject containing a file Makefile with this content: say_hello: Let's start by printing the classic 'Hello World' on the terminal. Before you start, ensure that make is installed in your system. In this article, we'll explore make and Makefile using basic and advanced examples. Most open source projects use make to compile a final executable binary, which can then be installed using make install.

You may have used make to compile a program from source code. The make utility requires a file, Makefile (or makefile), which defines set of tasks to be executed. If you want to run or update a task when certain files are updated, the make utility can come in handy.

Makefile for windows